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Process-induced skew reduction in nominal zero-skew clock trees., , and . ASP-DAC, page 84-89. IEEE, (2006)Non-uniform clock mesh optimization with linear programming buffer insertion., , and . DAC, page 74-79. ACM, (2010)Dynamic voltage scaling for SEU-tolerance in low-power memories., and . VLSI-SoC, page 207-212. IEEE, (2012)Current-mode clock distribution., and . ISCAS, page 1203-1206. IEEE, (2014)High-Performance, Low-Power Resonant Clocking: Embedded tutorial., and . ICCAD, page 742-745. ACM, (2012)Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor., , , , , , and . IEEE Trans. Computers, 54 (8): 998-1012 (2005)VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS., , and . ISQED, page 506-515. IEEE, (2012)DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2108-2117 (2018)Welcome from the general chair.. VLSI-SoC, IEEE, (2012)A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS., , and . ICCD, page 499-506. IEEE Computer Society, (2016)