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A Novel In-DRAM Accelerator Architecture for Binary Neural Network., , , и . COOL CHIPS, стр. 1-3. IEEE, (2020)$Q$ -Value Prediction for Reinforcement Learning Assisted Garbage Collection to Reduce Long Tail Latency in SSD., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2240-2253 (2020)An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design., , , , , , и . Des. Autom. Embed. Syst., 8 (2-3): 119-138 (2003)FPGA-based prototyping systems for emerging memory technologies., , , , и . RSP, стр. 115-120. IEEE, (2014)Selective refresh to avoid read disturb errors in STT-RAM main memory., и . ISOCC, стр. 315-316. IEEE, (2016)An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model., , и . ISLPED, стр. 84-87. ACM, (2002)Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes., , и . DAC, стр. 139:1-139:6. ACM, (2014)An industrial perspective of power-aware reliable SoC design., , и . ASP-DAC, стр. 555-557. IEEE, (2008)An FPGA-based platform for non volatile memory emulation., и . NVMSA, стр. 1-4. IEEE, (2017)Multi-scale Local Implicit Keypoint Descriptor for Keypoint Matching., , и . CVPR Workshops, стр. 6145-6154. IEEE, (2023)