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A Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache Architectures.

, , , , and . ICFEM, volume 13478 of Lecture Notes in Computer Science, page 190-208. Springer, (2022)

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An Event-based Compositional Reasoning Approach for Concurrent Reactive Systems., , , and . CoRR, (2018)Event-based formalization of safety-critical operating system standards: An experience report on ARINC 653 using Event-B., , , and . ISSRE, page 281-292. IEEE Computer Society, (2015)An Executable Formalisation of the SPARCv8 Instruction Set Architecture: A Case Study for the LEON3 Processor., , , , and . FM, volume 9995 of Lecture Notes in Computer Science, page 388-405. (2016)Model Checking C Programs with Dynamic Memory Allocation., , and . COMPSAC, page 219-226. IEEE Computer Society, (2008)Rely-Guarantee Reasoning About Concurrent Memory Management in Zephyr RTOS., and . CAV (2), volume 11562 of Lecture Notes in Computer Science, page 515-533. Springer, (2019)Verifying FreeRTOS' Cyclic Doubly Linked List Implementation: From Abstract Specification to Machine Code., , , , and . ICECCS, page 120-129. IEEE Computer Society, (2015)CSimpl: A Rely-Guarantee-Based Framework for Verifying Concurrent Programs., , , , , and . TACAS (1), volume 10205 of Lecture Notes in Computer Science, page 481-498. (2017)Towards Model Checking C Code with OPEN/CÆSAR., , and . MSVVEIS, page 198-201. INSTICC Press, (2006)Extending CADP for Analyzing C Code., , and . MSVVEIS, page 104-113. INSTICC PRESS, (2007)VeriFormal: An Executable Formal Model of a Hardware Description Language., , and . SG-CRC, volume 15 of Cryptology and Information Security Series, page 19-36. IOS Press, (2017)