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CaSym: Cache Aware Symbolic Execution for Side Channel Detection and Mitigation.

, , , , and . IEEE Symposium on Security and Privacy, page 505-521. IEEE, (2019)

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Using Task Recomputation During Application Mapping in Parallel Embedded Architectures., , and . CDES, page 29-35. CSREA Press, (2006)Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors., , , and . SoCC, page 77-78. IEEE, (2006)The design and use of simplepower: a cycle-accurate energy estimation tool., , , and . DAC, page 340-345. ACM, (2000)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)A compiler approach for reducing data cache energy., , , and . ICS, page 76-85. ACM, (2003)A Compiler Algorithm for Optimizing Locality in Loop Nests., , and . International Conference on Supercomputing, page 269-276. ACM, (1997)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters., , , , , and . CCGRID, page 131-141. IEEE, (2020)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)