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NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , and . DAC, page 534-539. ACM, (2008)A Boolean Paradigm in Multi-Valued Logic Synthesis., and . IWLS, page 173-177. (2002)Combinational techniques for sequential equivalence checking., , , and . FMCAD, page 145-149. IEEE, (2010)Automated Extraction of Inductive Invariants to Aid Model Checking., , and . FMCAD, page 165-172. IEEE Computer Society, (2007)Topologically constrained logic synthesis., , and . ICCAD, page 679-686. ACM / IEEE Computer Society, (2002)Practical Boolean Decomposition for Delay-driven LUT Mapping., , , and . CoRR, (2024)Invariant-Strengthened Elimination of Dependent State Elements., , , , and . FMCAD, page 1-9. IEEE, (2008)Incremental ATPG methods for multiple faults under multiple fault models., , , and . ISQED, page 177-180. IEEE, (2015)Rewriting Environment for Arithmetic Circuit Verification., , , , and . LPAR, volume 57 of EPiC Series in Computing, page 656-666. EasyChair, (2018)