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A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits., , and . ISCAS, IEEE, (2006)A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2641-2654 (2017)A frequency up-conversion and two-step channel selection embedded CMOS D/A interface., , , , and . ISCAS (1), page 392-395. IEEE, (2005)A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H., , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)New impulse sampled IIR switched-capacitor interpolators., , and . ICECS, page 203-206. IEEE, (1996)A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction., , and . ISCAS, page 177-180. IEEE, (2000)A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique., , , , , and . APCCAS, page 276-279. IEEE, (2008)A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators., , , , , and . APCCAS, page 29-32. IEEE, (2012)An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs., , , and . APCCAS, page 208-211. IEEE, (2010)