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Disambiguation of "Palomino, Daniel"

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4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding.

, , , , , , and . VCIP, page 132-135. IEEE, (2020)

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Reynaldo Linares-Palomino

Nicole Hillenbrand Palomino

Nahomi Castro-Palomino Laria

Julio Castro-Palomino Laria

Daniel

 

Other publications of authors with the same name

Speedup evaluation of HEVC parallel video coding using Tiles., , , and . J. Real Time Image Process., 17 (5): 1469-1486 (2020)A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard., , , and . SBCCI, page 1-6. IEEE, (2023)AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design., , , , , , , and . IEEE Open J. Circuits Syst., (2021)GPU-Acceleration of Affine Prediction in the Versatile Video Coding., , and . ISCAS, page 429-433. IEEE, (2022)Speedup-aware history-based tiling algorithm for the HEVC standard., , , and . ICIP, page 824-828. IEEE, (2016)Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders., , , , and . EUSIPCO, page 1-5. IEEE, (2019)Low-Complexity HEVC Transrating Based on Prediction Unit Mode Inheritance., , , , and . EUSIPCO, page 550-554. IEEE, (2020)Configurable Cache Memory Architecture for Low-Energy Motion Estimation., , , , , , , and . ISCAS, page 1-5. IEEE, (2018)Encoding Efficiency and Computational Cost Assessment of State-Of-The-Art Point Cloud Codecs., , , , and . ICIP, page 3726-3730. IEEE, (2019)Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction., , , , and . ISCAS, page 1808-1812. IEEE, (2022)