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Practical design assistance at register transfer level using a data path verifier.

, , , and . ICCD, page 99-102. IEEE Computer Society, (1990)

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A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio., , , and . CAV, volume 531 of Lecture Notes in Computer Science, page 76-85. Springer, (1990)Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement., , , , and . ISPD, page 31-39. ACM, (2024)Application of Boolean Unification to Combinational Logic Synthesis., , , and . ICCAD, page 510-513. IEEE Computer Society, (1991)Patching Method for Lookup-Table Type FPLs., and . FPL, volume 705 of Lecture Notes in Computer Science, page 61-70. Springer, (1992)A redesign technique for combinational circuits based on gate reconnections., , and . ICCAD, page 632-637. IEEE Computer Society / ACM, (1994)On convergence of switching windows computation in presence of crosstalk noise., , , and . ISPD, page 84-89. ACM, (2002)Exact Required Time Analysis via False Path Detection., and . DAC, page 220-225. ACM Press, (1997)VIS: A System for Verification and Synthesis., , , , , , , , , and 6 other author(s). CAV, volume 1102 of Lecture Notes in Computer Science, page 428-432. Springer, (1996)Practical design assistance at register transfer level using a data path verifier., , , and . ICCD, page 99-102. IEEE Computer Society, (1990)Combinational Verification based on High-Level Functional Specifications., , and . DATE, page 803-808. IEEE Computer Society, (1998)