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Disambiguation of "Steven, Gordon B."

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Cached Two-Level Adaptive Branch Predictors with Multiple Stages.

, , and . ARCS, volume 2299 of Lecture Notes in Computer Science, page 179-194. Springer, (2002)

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Steven B Jan

Gordon Krenz

Gordon Weinberg

Gordon Whittaker

Leo Gordon

 

Other publications of authors with the same name

Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture., and . Euro-Par, Vol. II, volume 1124 of Lecture Notes in Computer Science, page 779-788. Springer, (1996)Cached Two-Level Adaptive Branch Predictors with Multiple Stages., , and . ARCS, volume 2299 of Lecture Notes in Computer Science, page 179-194. Springer, (2002)An explicitly declared delayed-branch mechanism for a superscalar architecture., and . Microprocess. Microprogramming, 40 (10-12): 677-680 (1994)A superscalar architecture to exploit instruction level parallelism., , , , and . Microprocess. Microsystems, 20 (7): 391-400 (1997)Applying Caching to Two-Level Adaptive Branch Prediction., , , and . DSD, page 186-193. IEEE Computer Society, (2001)Static Scheduling for Out-of-order Instruction Issue Processors., , and . ACAC, page 90-96. IEEE Computer Society, (2000)Two-level branch prediction using neural networks., , , , , and . J. Syst. Archit., 49 (12-15): 557-570 (2003)The impact of cache organisation on the instruction issue rate of a superscalar processor., , and . PDP, page 58-65. IEEE Computer Society, (1999)Addressing mechanisms for VLIW and superscalar processors., , , , and . Microprocess. Microprogramming, 39 (2-5): 75-78 (1993)ALU design and processor branch architecture., and . Microprocess. Microprogramming, 36 (5): 259-278 (1993)