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Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 228-251 (2021)COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity., , , and . IEEE Trans. Inf. Forensics Secur., (2020)Can Overclocking Detect Hardware Trojans?, , , and . ISCAS, page 1-5. IEEE, (2021)Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links., , and . VLSID, page 371-376. IEEE, (2019)ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis., , , and . VLSID, page 410-415. IEEE Computer Society, (2018)RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators., , , , and . ITC, page 504-508. IEEE, (2022)Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators., , and . ISQED, page 343-348. IEEE, (2021)Bottlenecks in Secure Adoption of Deep Neural Networks in Safety-Critical Applications., , and . MWSCAS, page 801-805. IEEE, (2023)Towards High-Level Synthesis of Quantum Circuits., , and . DATE, page 1-6. IEEE, (2023)Efficient Trace Signal Selection for Post Silicon Validation and Debug., and . VLSI Design, page 352-357. IEEE Computer Society, (2011)