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Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI., , , , и . VLSI-SoC (Selected Papers), том 500 из IFIP Advances in Information and Communication Technology, стр. 1-21. Springer, (2017)Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths., , , , , , и . PDP, стр. 143-147. IEEE, (2021)A Case for Low-Latency Network-on-Chip using Compression Routers., , , и . PDP, стр. 134-142. IEEE, (2021)An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings., , и . PDP, стр. 1-9. IEEE, (2022)Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops., , , , , , , , и . MCSoC, стр. 273-280. IEEE, (2021)Board Allocation Algorithm for the Resource Management System of FiC., , и . MCSoC, стр. 218-224. IEEE, (2023)Distance Aware Compression for Low Latency High Bandwidth Interconnection Network., , и . MCSoC, стр. 361-367. IEEE, (2022)The impact of output selection function on adaptive routing., , , и . CATA, стр. 241-246. ISCA, (2001)Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel., и . CANDAR Workshops, стр. 280-284. IEEE, (2019)A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration., , и . MCSoC, стр. 32-37. IEEE, (2019)