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Disambiguation of "Takizawa, Hiroyuki"

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An energy optimization method for vector processing mechanisms.

, , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2014)

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Hiroyuki Tan

Hiroyuki Kobayashi

Chieko Takizawa

Hiroyuki Okamuro

Hiroyuki Takada

 

Other publications of authors with the same name

A Method for Reducing Time-to-Solution in Quantum Annealing Through Pausing., and . HPC Asia, page 137-145. ACM, (2022)neoSYCL: a SYCL implementation for SX-Aurora TSUBASA., , and . HPC Asia, page 50-57. ACM, (2021)Evaluating I/O Acceleration Mechanisms of SX-Aurora TSUBASA., , , and . IPDPS Workshops, page 752-759. IEEE, (2021)A memory bank conflict prevention mechanism for SYCL on SX-Aurora TSUBASA., , , and . CANDAR (Workshops), page 217-222. IEEE, (2021)Improving the Accuracy in SpMV Implementation Selection with Machine Learning., , , , and . CANDAR (Workshops), page 172-177. IEEE, (2020)Performance Evaluation of a Next-Generation SX-Aurora TSUBASA Vector Supercomputer., , , , , , and . ISC, volume 13948 of Lecture Notes in Computer Science, page 359-378. Springer, (2023)A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs., , , and . MEDEA@PACT, page 113-120. ACM, (2007)Modeling of cache access behavior based on Zipf's law., , , and . MEDEA@PACT, page 9-15. ACM, (2008)A Real-time Flood Inundation Prediction on SX-Aurora TSUBASA., , , , , , , and . HIPC, page 192-197. IEEE, (2022)Design and evaluation of a media-oriented vector processor with a multi-banked cache memory., , , , and . ESTIMedia, page 78-87. IEEE, (2013)