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Accurate off-line phase classification for HW/SW co-designed processors.

, , , and . Conf. Computing Frontiers, page 5:1-5:10. ACM, (2014)

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Cache organizations for clustered microarchitectures., , and . WMPI, page 46-55. ACM, (2004)Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment., , and . HPCC/EUC, page 518-525. IEEE, (2013)A framework for modeling and optimization of prescient instruction prefetch., , , , , , and . SIGMETRICS, page 13-24. ACM, (2003)Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors., , and . MICRO, page 315-325. IEEE Computer Society, (2003)Ultra-low power render-based collision detection for CPU/GPU systems., , , and . MICRO, page 445-456. ACM, (2015)Value Prediction for Speculative Multithreaded Architectures., , and . MICRO, page 230-236. ACM/IEEE Computer Society, (1999)Near-Optimal Padding for Removing Conflict Misses., , and . LCPC, volume 2481 of Lecture Notes in Computer Science, page 329-343. Springer, (2002)A Low-Power Hardware Accelerator for ORB Feature Extraction in Self-Driving Cars., , and . SBAC-PAD, page 11-21. IEEE, (2021)Boosting single-thread performance in multi-core systems through fine-grain multi-threading., , , , , , , and . ISCA, page 474-483. ACM, (2009)Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic., , and . MASCOTS, page 439-448. IEEE Computer Society, (2012)