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Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip., , and . CODES+ISSS, page 481-490. ACM, (2009)Demonstration of a Time-predictable Flight Controller on a Multicore Processor., , , , , , and . ISORC, page 95-96. IEEE, (2019)Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting., , , , , , , , and . MLSP, page 1-6. IEEE, (2023)A Time-Predictable Memory Network-on-Chip., , , and . WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip., , , and . SoC, page 171-174. IEEE, (2005)Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools., , , and . NORCHIP, page 1-6. IEEE, (2014)Interfacing hardware accelerators to a time-division multiplexing network-on-chip., , , and . NORCAS, page 1-4. IEEE, (2015)ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology., and . NOCS, page 55-64. IEEE Computer Society, (2008)Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements., , and . DSD, page 168-175. IEEE, (2023)Future directions in clocking multi-ghz systems., and . ISLPED, page 219. ACM, (2002)