Author of the publication

An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration.

, , , and . IEEE J. Solid State Circuits, 57 (5): 1480-1491 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems., , and . ISCAS (1), page 320-323. IEEE, (2001)A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems., , and . ISCAS (1), page 369-372. IEEE, (2004)Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity., , and . ISCAS (2), page 57-60. IEEE, (1999)Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output., , , and . ISCAS (1), page 129-132. IEEE, (2003)A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique., , and . APCCAS, page 183-186. IEEE, (2006)SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit., , , and . ISCAS, page 1276-1279. IEEE, (2010)A 1.83 μW, 0.78 μVrms input referred noise neural recording front end., , , and . ISCAS, page 405-408. IEEE, (2013)A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW., , , and . ISSCC, page 368-370. IEEE, (2012)16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration., , , , , and . ISSCC, page 282-283. IEEE, (2017)A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet., , , and . A-SSCC, page 1-4. IEEE, (2015)