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Efficient tree topology for FPGA interconnect network.

, , , and . ACM Great Lakes Symposium on VLSI, page 321-326. ACM, (2008)

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Implementation of Scalable Embedded FPGA for SOC., , , and . ReCoSoC, page 59-62. Univ. Montpellier II, (2005)Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis., , and . NEWCAS, page 1-4. IEEE, (2013)Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology., , and . 3DIC, page 1-8. IEEE, (2013)Customizable DSP architecture for ASIP core design., and . ISCAS (4), page 302-305. IEEE, (2001)A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic., , and . ISCAS (4), page 878-881. IEEE, (2001)Performances improvement of FPGA using novel multilevel hierarchical interconnection structure., , , and . ICCAD, page 675-679. ACM, (2006)A multilevel hierarchical interconnection structure for FPGA., , , and . FPGA, page 225. ACM, (2006)Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only)., , and . FPGA, page 251. ACM, (2014)Efficient tree topology for FPGA interconnect network., , , and . ACM Great Lakes Symposium on VLSI, page 321-326. ACM, (2008)Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist., , , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 221. Springer, (2013)