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Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC.

, , and . DATE, page 1420-1425. IEEE, (2020)

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Strengthening Post-Quantum Security for Automotive Systems., , and . DSD, page 570-576. IEEE, (2020)Secure and Compact Full NTRU Hardware Implementation., , , , and . VLSI-SoC, page 89-94. IEEE, (2018)RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography., , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020 (4): 239-280 (2020)Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers., , and . ICCAD, page 35:1-35:9. IEEE, (2020)The Influence of LWE/RLWE Parameters on the Stochastic Dependence of Decryption Failures., , and . ICICS, volume 12282 of Lecture Notes in Computer Science, page 331-349. Springer, (2020)Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography., and . HOST, page 141-150. IEEE, (2019)Error-Correcting Codes for Lattice-Based Key Exchange.. Krypto-Tag, Gesellschaft für Informatik e.V. / FG KRYPTO, (2018)Towards Secure Coprocessors and Instruction Set Extensions for Acceleration of Post-Quantum Cryptography.. Technical University of Munich, Germany, (2022)Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC., , and . DATE, page 1420-1425. IEEE, (2020)Post-Quantum Signatures on RISC-V with Hardware Acceleration., , , and . IACR Cryptol. ePrint Arch., (2022)