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The effect of cache models on iterative compilation for combined tiling and unrolling., , , and . Concurr. Comput. Pract. Exp., 16 (2-3): 247-270 (2004)Obituary: Peter Knijnenburg (1961-2007)., and . Concurr. Comput. Pract. Exp., 21 (1): 5 (2009)IATAC: a smart predictor to turn-off L2 cache lines., , , and . ACM Trans. Archit. Code Optim., 2 (1): 55-77 (2005)Merge or Separate?: Multi-job Scheduling for OpenCL Kernels on CPU/GPU Platforms., and . GPGPU@PPoPP, page 22-31. ACM, (2017)Neural architecture search as program transformation exploration., , and . ASPLOS, page 915-927. ACM, (2021)Compiler Directed Early Register Release., , , , and . IEEE PACT, page 110-122. IEEE Computer Society, (2005)Compiler Reduction of Synchronisation in Shared Virtual Memory Systems., and . International Conference on Supercomputing, page 318-327. ACM, (1995)DLAS: An Exploration and Assessment of the Deep Learning Acceleration Stack., , , , and . CoRR, (2023)Loop Rolling for Code Size Reduction., , , , and . CGO, page 217-229. IEEE, (2022)Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design., , , , , , , , , and 7 other author(s). HPCA, page 654-667. IEEE, (2021)