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RecoNoC: A reconfigurable network-on-chip., , , , and . ReCoSoC, page 1-2. IEEE, (2011)Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS., , and . FPL, page 1-7. IEEE, (2013)Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS., , , , and . FPL, page 1-8. IEEE, (2013)Modeling multiple autonomous robot behaviors and behavior switching with a single reservoir computing network., , and . SMC, page 1843-1848. IEEE, (2008)MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement., , and . FPGA, page 184. ACM, (2019)Superimposed in-circuit debugging for self-healing FPGA overlays., and . LATS, page 1-6. IEEE, (2018)Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip., and . ReConFig, page 1-8. IEEE, (2014)The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks., and . ReConFig, page 1-6. IEEE, (2013)Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations., , , , , and . Trans. High Perform. Embed. Archit. Compil., (2007)Enabling FPGA routing configuration sharing in dynamic partial reconfiguration., , , , and . Des. Autom. Embed. Syst., 19 (1-2): 189-221 (2015)