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A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS.

X. Zhao, Y. Chen, P. Mak, and R. Martins. CICC, page 1-4. IEEE, (2020)

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Ellen Mak

Beatrice Puiu

Rebecca Mak

Kwok Mak

Ale PuÌ

Other publications of authors with the same name

Micropower two-stage amplifier employing recycling current-buffer Miller compensation.W. Wang, Z. Yan, P. Mak, M. Law, and R. Martins. ISCAS, page 1889-1892. IEEE, (2014)26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop.G. Qi, P. Mak, and R. Martins. ISSCC, page 452-454. IEEE, (2016)An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners.P. Mak, K. Ieong, and R. Martins. ISCAS, page 668-671. IEEE, (2008)A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance.M. Martins, P. Mak, and R. Martins. ISCAS, page 289-292. IEEE, (2011)Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques.M. Li, C. Ieong, M. Law, P. Mak, M. Vai, S. Pun, and R. Martins. IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3119-3123 (2015)A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS.P. Mak, and R. Martins. IEEE J. Solid State Circuits, 46 (9): 1970-1984 (2011)Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters.Y. Jiang, M. Law, P. Mak, and R. Martins. IEEE J. Solid State Circuits, 53 (12): 3455-3469 (2018)A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop.G. Qi, P. Mak, and R. Martins. IEEE J. Solid State Circuits, 52 (8): 2055-2070 (2017)A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays.K. Lei, H. Heidari, P. Mak, M. Law, F. Maloberti, and R. Martins. IEEE J. Solid State Circuits, 52 (1): 284-297 (2017)A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.Z. Yang, Y. Chen, P. Mak, and R. Martins. A-SSCC, page 283-284. IEEE, (2019)