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A Platform for the Development and the Validation of HW IP Components Starting from Reference Software Specifications.

, , and . EURASIP J. Embed. Syst., (2008)

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Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework., , , and . SiPS, page 293-298. IEEE, (2008)A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning., and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 485-494. Springer, (2007)Reconfigurable Media Coding: A New Specification Model for Multimedia Coders., , , and . SiPS, page 481-486. IEEE, (2007)Optimization methodologies for complex FPGA-based signal processing systems with CAL., , , , and . DASIP, page 192-199. IEEE, (2011)A Platform for the Development and the Validation of HW IP Components Starting from Reference Software Specifications., , and . EURASIP J. Embed. Syst., (2008)"Motion Estimation Accelerator with User Search Strategy in an RVC Context"., , , , and . ICIP, page 761-764. IEEE, (2009)A Hybrid Decoder Configuration of MPEG-4 and AVS in Reconfigurable Video Coding Framework., , , and . ISCAS, page 1935. IEEE, (2009)Methodology and technique to improve throughput of FPGA-based Cal dataflow programs: Case study of the RVC MPEG-4 SP Intra decoder., , , , and . SiPS, page 186-191. IEEE, (2011)High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms., , and . DASIP, page 191-198. IEEE, (2010)Reconfigurable video coding: Objectives and technologies., , and . ICIP, page 749-752. IEEE, (2009)