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Bit-Slicing FPGA Accelerator for Quantized Neural Networks.

O. Bilaniuk, S. Wagner, Y. Savaria, and J. David. ISCAS, page 1-5. IEEE, (2019)

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Yvon Gauthier

Yvon Gardan

Other publications of authors with the same name

Joint power control and beamformer design with antenna selection.F. Hoque, Y. Savaria, and C. Cardinal. CCECE, page 1-4. IEEE, (2017)Vt-conscious repeater insertion in power-managed VLSI.H. Zarrabi, A. Al-Khalili, and Y. Savaria. ISIC, page 99-102. IEEE, (2014)High-voltage operational amplifier based on dual floating-gate transistors.Z. Huang, Y. Savaria, M. Sawan, and R. Meinga. ISCAS, IEEE, (2006)Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain.Y. Blaquière, Y. Basile-Bellavance, S. Berrima, and Y. Savaria. ISCAS, page 2559-2562. IEEE, (2014)Fast parameters optimization of an iterative decoder using a configurable hardware accelerator.G. Provost, M. Cantin, M. Sawan, C. Cardinal, Y. Savaria, and D. Haccoun. ISCAS (4), page 4159-4162. IEEE, (2005)Spurs modeling in direct digital period synthesizers related to phase accumulator truncation.B. Izouggaghen, A. Khouas, and Y. Savaria. ISCAS (3), page 389-392. IEEE, (2004)Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.H. Bui, and Y. Savaria. ISCAS (4), page 369-372. IEEE, (2004)An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).T. Luinaud, Y. Savaria, and J. Langlois. FPGA, page 287-288. ACM, (2017)Multiple categorization using fuzzy ART.P. Lavoie, J. Crespo, and Y. Savaria. ICNN, page 1983-1988. IEEE, (1997)AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology.M. Fiorentino, C. Thibeault, Y. Savaria, F. Gagnon, T. Awad, D. Morrissey, and M. Laurence. ASYNC, page 58-59. IEEE, (2019)

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Disambiguation of "Savaria, Yvon"

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Bit-Slicing FPGA Accelerator for Quantized Neural Networks.

Please choose a person to relate this publication to

Yvon Gauthier

Yvon Gardan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Savaria, Yvon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Bit-Slicing FPGA Accelerator for Quantized Neural Networks.

Please choose a person to relate this publication to

Yvon Gauthier

Yvon Gardan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Bit-Slicing FPGA Accelerator for Quantized Neural Networks.