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Considering the effect of process variations during the ISA extension design flow., , , и . Microprocess. Microsystems, 37 (6-7): 713-724 (2013)A 65nm 10GHz pipelined MAC structure., , и . ISCAS, стр. 460-463. IEEE, (2008)Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions., , , и . ACM Trans. Design Autom. Electr. Syst., 21 (2): 28:1-28:25 (2016)Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture., , , и . J. Real-Time Image Processing, 8 (4): 421-435 (2013)Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence., , и . DATE, стр. 1340-1345. ACM, (2008)On-Chip Verification of NoCs Using Assertion Processors., , , , и . DSD, стр. 535-538. IEEE Computer Society, (2007)Assertion based design error diagnosis for core-based SoCs., , , и . SoCC, стр. 269-272. IEEE, (2007)Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems., , , , и . NoCArc@MICRO, стр. 45-50. ACM, (2016)An efficient temperature dependent hot carrier injection reliability simulation flow., , , , и . Microelectron. Reliab., (2016)A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor., , и . ICECS, стр. 119-122. IEEE, (2006)