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Disambiguation of "Ruiz, Juan-Carlos"

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Black Hole Attack Injection in Ad hoc Networks

, , , and . Fault Tolerance Systems Group (GSTF), Instituto de las TIC Avanzadas (ITACA) Universidad Politécnica de Valencia, Campus de Vera s/n, E-46022, Valencia, Spain, (2008)

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Juan Ramirez Ruiz

Juan Carlos Ulacia

Juan Carlos Palazuelos

Juan Carlos Linares

Juan Carlos Wuhrmann

 

Other publications of authors with the same name

Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems., , and . EDCC, page 1-8. IEEE, (2020)Design and Deployment of a Generic ECC-based Fault Tolerance Mechanism for Embedded HW Cores., , and . ETFA, page 1-8. IEEE, (2009)Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection., , and . LADC, page 97-106. IEEE, (2018)Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments., , , and . FPL, page 292-299. IEEE, (2012)A Multi-Criteria Analysis of Benchmark Results With Expert Support for Security Tools., , , , and . IEEE Trans. Dependable Secur. Comput., 19 (4): 2151-2164 (2022)Technologies for the Development of Dependable and Secure Component-based Embedded Systems: TecnoSeC Project., , , and . ESA, page 237-242. CSREA Press, (2009)Towards changing the user perception of mobile communications through geotagged information., , , , and . ARMOR, page 5:1-5:6. ACM, (2012)Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection., , and . EDCC, page 1-8. IEEE Computer Society, (2018)Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level., , and . EDCC, page 10-17. IEEE Computer Society, (2017)Ultrafast Error Correction Codes for Double Error Detection/Correction., , , , , and . EDCC, page 108-119. IEEE Computer Society, (2016)