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SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling., , , , , , and . HPCA, page 333-346. IEEE, (2023)TWiCe: preventing row-hammering by exploiting time window counters., , , , and . ISCA, page 385-396. ACM, (2019)TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory., , , , , and . MICRO, page 268-281. ACM, (2021)MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks., , , , , , , , , and . IEEE Trans. Computers, 69 (7): 955-967 (2020)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , and 6 other author(s). ISCA, page 43-56. IEEE, (2021)Work as a team or individual: Characterizing the system-level impacts of main memory partitioning., , , , , and . IISWC, page 156-166. IEEE Computer Society, (2017)Graphene: Strong yet Lightweight Row Hammer Protection., , , , , and . MICRO, page 1-13. IEEE, (2020)CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention., , and . IEEE Access, (2020)Accelerating Fully Homomorphic Encryption Through Microarchitecture-Aware Analysis and Optimization., , , , , , , and . ISPASS, page 237-239. IEEE, (2021)GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent., , , , , , , , and . HPCA, page 249-262. IEEE, (2021)