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A 60GHz CMOS Receiver Using a 30GHz LO., and . ISSCC, page 190-191. IEEE, (2008)A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply., , and . VLSIC, page 66-. IEEE, (2015)A 10b 500MHz 55mW CMOS ADC., and . ISSCC, page 84-85. IEEE, (2009)A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance., , and . VLSI Circuits, page 271-272. IEEE, (2018)A Harmonic-Rejecting CMOS LNA for Broadband Radios., and . IEEE J. Solid State Circuits, 48 (4): 1072-1084 (2013)Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems., and . DAC, page 121-126. ACM, (2001)Problem of timing mismatch in interleaved ADCs.. CICC, page 1-8. IEEE, (2012)A new receiver architecture for multiple-antenna systems., and . CICC, page 357-360. IEEE, (2005)An 8-bit 150-MHz CMOS A/D converter., and . IEEE J. Solid State Circuits, 35 (3): 308-317 (2000)A 2-GHz, 6-mW BiCMOS frequency synthesizer., and . IEEE J. Solid State Circuits, 30 (12): 1457-1462 (December 1995)