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Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2221-2232 (2015)

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Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2221-2232 (2015)FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training., , and . DSD, page 381-388. IEEE Computer Society, (2018)Power optimal Network-on-Chip interconnect design., , and . SoCC, page 147-150. IEEE, (2009)HD Resolution Intra Prediction Architecture for H.264 Decoder., , and . VLSI Design, page 107-112. IEEE Computer Society, (2012)In-channel Flow Control Scheme for Network-on-Chip., and . DSD, page 459-466. IEEE Computer Society, (2010)Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking., , , and . AIR, page 61:1-61:6. ACM, (2023)Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA., , and . DSD, page 340-343. IEEE, (2020)Transparent FPGA based device for SQL DDoS mitigation., , and . FPT, page 82-89. IEEE, (2013)A scalable network port scan detection system on FPGA., , and . FPT, page 1-6. IEEE, (2011)Network Emulation For Tele-driving Application Development., , , , , , , , , and . COMSNETS, page 109-110. IEEE, (2021)