( en | de | ru )

 

Disambiguation of "Pan, David Z."

Author of the publication

copydeleteadd this publication to your clipboard
On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.

, , , , and . IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David Tse-chien Pan

Z Taufig

Petra Pan

Xiaoqing Pan

Weiqing Pan

 

Other publications of authors with the same name

A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization., , , , , and . ACM Great Lakes Symposium on VLSI, page 87-90. ACM, (2015)On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes., , , , and . IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 185-196 (2010)OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1618-1629 (2016)