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Disambiguation of "Lee, Seon-Kyoo"

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A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.

, , , , and . CICC, page 1-4. IEEE, (2012)

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Kyoo-Sik Lee

Myung-Seon Lee

Young-Seon Lee

Seon-Guan Lee

Hyo-Seon Lee

 

Other publications of authors with the same name

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface., , , and . IEEE J. Solid State Circuits, 46 (3): 651-659 (2011)A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS., , , and . IEEE J. Solid State Circuits, 45 (12): 2874-2881 (2010)A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 56 (4): 1129-1140 (2021)A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition., , , and . J. Electr. Comput. Eng., (2011)A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (2): 70-74 (2011)A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 840-844 (2014)A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling., , , , and . CICC, page 1-4. IEEE, (2012)A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL., , , and . IEEE J. Solid State Circuits, 46 (2): 435-444 (2011)A 95fJ/b current-mode transceiver for 10mm on-chip interconnect., , , , and . ISSCC, page 262-263. IEEE, (2013)A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation., , , and . ISSCC, page 140-142. IEEE, (2012)