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Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.

L. Hoang, A. Daus, S. Wahid, J. Kwon, J. Ko, S. Qin, M. Islam, K. Saraswat, H. Wong, and E. Pop. DRC, page 1-2. IEEE, (2022)

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Horst S H Seifert

Cyrano S H Bergmann

Horst S H Seifert

Guenther H S Mueller

Horst S H Seifert

Other publications of authors with the same name

Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor.M. Li, C. Hsu, S. Shen, A. Chou, Y. Lin, C. Chuu, N. Yang, S. Chou, L. Huang, C. Cheng and 7 other author(s). VLSI Technology and Circuits, page 290-291. IEEE, (2022)The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology.H. Wong. DRC, page 1-2. IEEE, (2018)Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters.S. Bohaichuk, M. Munoz-Rojo, G. Pitner, C. McClellan, F. Lian, J. Li, J. Jeong, M. Samant, S. Parkin, H. Wong and 1 other author(s). DRC, page 1-2. IEEE, (2018)Contact pitch and location prediction for Directed Self-Assembly template verification.Z. Xiao, Y. Du, M. Wong, H. Yi, H. Wong, and H. Zhang. ASP-DAC, page 644-651. IEEE, (2015)On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators.H. Li, M. Bhargava, P. Whatmough, and H. Wong. DAC, page 131. ACM, (2019)Nano-engineered architectures for ultra-low power wireless body sensor nodes.R. Braojos, D. Atienza, M. Aly, T. Wu, H. Wong, S. Mitra, and G. Ansaloni. CODES+ISSS, page 23:1-23:10. ACM, (2016)Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices.S. Eryilmaz, D. Kuzum, R. Jeyasingh, S. Kim, M. BrightSky, C. Lam, and H. Wong. CoRR, (2014)Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design.S. Oh, J. Park, S. Wong, and H. Wong. ISQED, page 342-346. IEEE, (2010)Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.N. Patil, A. Lin, J. Zhang, H. Wong, and S. Mitra. DAC, page 304-309. ACM, (2009)CMOS scaling into the 21st century: 0.1 µm and beyond.Y. Taur, Y. Mii, D. Frank, H. Wong, D. Buchanan, S. Wind, S. Rishton, W. Sai-Halasz, and E. Nowak. IBM J. Res. Dev., 39 (1-2): 245-260 (1995)

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Disambiguation of "Wong, H.-S. Philip"

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Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.

Please choose a person to relate this publication to

Horst S H Seifert

Cyrano S H Bergmann

Horst S H Seifert

Guenther H S Mueller

Horst S H Seifert

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wong, H.-S. Philip"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.

Please choose a person to relate this publication to

Horst S H Seifert

Cyrano S H Bergmann

Horst S H Seifert

Guenther H S Mueller

Horst S H Seifert

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties.