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Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches., , , and . Microprocess. Microsystems, (2016)Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience., , , and . DATE, page 382-387. IEEE, (2022)Quantifying the Impact of Monolithic 3D (M3D) Integration on L1 Caches., , and . IEEE Trans. Emerg. Top. Comput., 9 (2): 854-865 (2021)ZEC ECC: A Zero-Byte Eliminating Compression-Based ECC Scheme for DRAM Reliability., , , , and . IEEE Access, (2024)Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience., , , and . DATE, page 1-6. IEEE, (2023)An efficient trade-off between yield and energy for eDRAM caches under process variations., and . Microprocess. Microsystems, (2017)Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture.. IEEE Access, (2021)Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency., , , , and . ISLPED, page 1-6. IEEE, (2019)Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory., , , , , and . HPCA, page 139-155. IEEE, (2024)Sparrow ECC: A Lightweight ECC Approach for HBM Refresh Reduction towards Energy-efficient DNN Inference., , , , and . ISLPED, page 1-6. ACM, (2024)