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Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

, , , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2657-2663 (2023)

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Dheera Venkatraman

Rishi Ramakrishnan

Muniarajan Ramakrishnan

Chinnaswamy Ramakrishnan

Ayyappan Ramakrishnan

 

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