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Disambiguation of "Park, Sang Phill"

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A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.

, , , and . ISSCC, page 388-389. IEEE, (2008)

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Sang-Min Park

Sang-Min Park

No-Sang Park

Sang Hyeun Park

Sang Wong Park

 

Other publications of authors with the same name

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture., , , , and . DAC, page 492-497. ACM, (2012)Layout-aware optimization of stt mrams., , , and . DATE, page 1455-1458. IEEE, (2012)IMPACT: imprecise adders for low-power approximate computing., , , , and . ISLPED, page 409-414. IEEE/ACM, (2011)Process variation tolerant SRAM array for ultra low voltage applications., , , and . DAC, page 108-113. ACM, (2008)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)Analysis and design of ultra low power thermoelectric energy harvesting systems., , , and . ISLPED, page 183-188. ACM, (2010)Stage number optimization for switched capacitor power converters in micro-scale energy harvesting., , , and . DATE, page 770-775. IEEE, (2011)Write-optimized reliable design of STT MRAM., , , , and . ISLPED, page 3-8. ACM, (2012)NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?, , , and . ASP-DAC, page 726-731. IEEE, (2008)A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)