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A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , and . VLSIC, page 346-. IEEE, (2015)A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter., , , , , , , , , and 4 other author(s). CICC, page 1-2. IEEE, (2023)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)Strong injection locking of low-Q LC oscillators., , , , , , , and . CICC, page 699-702. IEEE, (2008)Noise-Tolerant Digital System Design. University of Illinois Urbana-Champaign, USA, (2004)A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC., , , , , , , , , and . ECOC, page 1-3. IEEE, (2021)26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 440-441. IEEE, (2014)A 106 Gb/s 2.5 Vppd Linear Microring Modulator Driver with Integrated Photocurrent Sensor in 28nm CMOS., , , , , , and . OFC, page 1-3. IEEE, (2022)Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links., and . ICCD, page 254-260. IEEE Computer Society, (2003)A noise-tolerant dynamic circuit design technique., and . CICC, page 425-428. IEEE, (2000)