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Error Correction Schemes with Erasure Information for Fast Memories., , and . J. Electron. Test., 30 (2): 183-192 (2014)System-level hardware-based protection of memories against soft-errors., , , , and . DATE, page 1222-1225. IEEE, (2009)Error prediction based on concurrent self-test and reduced slack time., , , , and . DATE, page 1626-1631. IEEE, (2011)Shadow-scan design with low latency overhead and in-situ slack-time monitoring., , , , , , and . ETS, page 1-6. IEEE, (2014)Efficient Pattern Mapping for Deterministic Logic BIST., , , , , and . ITC, page 48-56. IEEE Computer Society, (2004)Error-correction schemes with erasure information for fast memories., and . ETS, page 1-6. IEEE Computer Society, (2013)Memory reliability improvements based on maximized error-correcting codes., , and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Synthesis of irregular combinational functions with large don't care sets., , , , and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2007)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection., , , , and . DATE, page 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Programmable restricted SEC codes to mask permanent faults in semiconductor memories., , and . IOLTS, page 147-153. IEEE Computer Society, (2010)