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A Coarse-Grain Phased Logic CPU., , and . IEEE Trans. Computers, 54 (7): 788-799 (2005)Generalized Early Evaluation in Self-Timed Circuits., , , and . DATE, page 255-259. IEEE Computer Society, (2002)PLFire: A Visualization Tool for Asynchronous Phased Logic Designs., , and . DATE, page 11096-11097. IEEE Computer Society, (2003)Setting the stage for CE2016: A revised body of knowledge., , , , , , and . FIE, page 1-4. IEEE Computer Society, (2014)Cooperative and progressive design experience for embedded systems., , and . IEEE Trans. Educ., 47 (1): 83-92 (2004)A Comparison of Synchronous and Asynchronous FSMD Designs., , and . ICCD, page 178-182. IEEE Computer Society, (1993)CE2016: Updated computer engineering curriculum guidelines., , , , , , , , , and . FIE, page 1-2. IEEE Computer Society, (2015)Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation., , and . ICCD, page 18-23. IEEE Computer Society, (2001)User-configurable experimental design flows on the web: the ISCAS'99 experiments., , and . ISCAS (6), page 440-443. IEEE, (1999)A Fine-Grain Phased Logic CPU., , and . ISVLSI, page 70-79. IEEE Computer Society, (2003)