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Disambiguation of "Rebeiro, Chester"

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IPA: an Instruction Profiling-Based Micro-architectural Side-Channel Attack on Block Ciphers.

, , , , and . J. Hardw. Syst. Secur., 3 (1): 26-44 (2019)

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Alexander Chester

Andrew Chester

Chester Avilés

William Chester Tepper

 

Other publications of authors with the same name

High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms., and . INDOCRYPT, volume 5365 of Lecture Notes in Computer Science, page 376-388. Springer, (2008)XFC: A Framework for eXploitable Fault Characterization in Block Ciphers., , and . DAC, page 8:1-8:6. ACM, (2017)Shakti-T: A RISC-V Processor with Light Weight Security Extensions., , , , and . HASP@ISCA, page 2:1-2:8. ACM, (2017)Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER., , , , and . IEEE Comput. Archit. Lett., 19 (1): 9-12 (2020)D-TIME: Distributed Threadless Independent Malware Execution for Runtime Obfuscation., , and . WOOT @ USENIX Security Symposium, USENIX Association, (2019)Pinpointing Cache Timing Attacks on AES., , and . VLSI Design, page 306-311. IEEE Computer Society, (2010)Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs., , and . DATE, page 1231-1236. IEEE, (2011)GANDALF: A fine-grained hardware-software co-design for preventing memory attacks., , , and . CoRR, (2017)A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms., , and . DSD, page 553-559. IEEE Computer Society, (2012)SHAKTI-MS: a RISC-V processor for memory safety in C., , , , and . LCTES, page 19-32. ACM, (2019)