( en | de | ru )

 

Disambiguation of "Devta-Prasanna, Narendra"

Author of the publication

copydeleteadd this publication to your clipboard
Detection of Internal Stuck-open Faults in Scan Chains.

, , , , and . ITC, page 1-10. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Narendra Kumar

Narendra Jussien

Narendra Panday

Narendra Solanki

Prasanna Rajagopalan

 

Other publications of authors with the same name

Multiple fault activation cycle tests for transistor stuck-open faults., , , and . ITC, page 821. IEEE Computer Society, (2010)An Enhanced Logic BIST Architecture for Online Testing., , , , and . IOLTS, page 10-15. IEEE Computer Society, (2008)Effective and Efficient Test Pattern Generation for Small Delay Defect., , and . VTS, page 111-116. IEEE Computer Society, (2009)Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells., , , , and . DFT, page 394-402. IEEE Computer Society, (2008)Improving the Detectability of Resistive Open Faults in Scan Cells., , , , and . DFT, page 383-391. IEEE Computer Society, (2009)Detection of Internal Stuck-open Faults in Scan Chains., , , , and . ITC, page 1-10. IEEE Computer Society, (2008)Detectability of internal bridging faults in scan chains., , , , and . ASP-DAC, page 678-683. IEEE, (2009)A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals., , , , and . ICCD, page 471-474. IEEE Computer Society, (2005)Test Generation for Open Defects in CMOS Circuits., , , , and . DFT, page 41-49. IEEE Computer Society, (2006)A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults., , , , and . ETS, page 185-192. IEEE Computer Society, (2006)