( en | de | ru )

 

Disambiguation of "McCanny, John V."

Author of the publication

copydeleteadd this publication to your clipboard
Linear QR Architecture for a Single Chip Adaptive Beamformer.

, , , and . VLSI Signal Processing, 24 (1): 67-81 (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

V Geoffroy

V Saile

V Wittwer

V Fendrich

V Adams

 

Other publications of authors with the same name

An efficient architecture for the 2-D biorthogonal discrete wavelet transform., , and . ICIP (3), page 314-317. IEEE, (2001)Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS"., , and . VLSI Signal Processing, 16 (1): 41-55 (1997)A 64-point Fourier transform chip for video motion compensation using phase correlation., , , and . IEEE J. Solid State Circuits, 31 (11): 1751-1761 (1996)A mixed cost-function adaptive algorithm for ADSL time-domain equalization., and . ICC, page 1798-1802. IEEE, (2002)A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems., and . ICASSP, page 4183. IEEE, (2002)Online CORDIC algorithm and VLSI architecture for implementing QR-array processors., , and . IEEE Trans. Signal Process., 48 (2): 592-598 (2000)A high speed CMOS/SOS implementation of a bit level systolic correlator., , , , and . ICASSP, page 1161-1164. IEEE, (1986)A VLSI architecture for multiplication, division and square root., and . ICASSP, page 1205-1208. IEEE Computer Society, (1991)Systolic IIR filters with bit level pipelining., , , and . ICASSP, page 2072-2075. IEEE, (1988)From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems.. DSP, page 16. IEEE, (2007)