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The design of random-testable sequential circuits.. FTCS, page 110-117. IEEE Computer Society, (1989)Minimized Power Consumption for Scan-Based BIST., and . J. Electron. Test., 16 (3): 203-212 (2000)Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen, , , , and . VDI-Buch Springer Berlin Heidelberg, Berlin, Heidelberg, (2009)Introduction., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 397-398 (2003)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)Synthesis of IDDQ-testable circuits: integrating built-in current sensors., , , , and . ED&TC, page 573-580. IEEE Computer Society, (1995)Fast controllers for data dominated applications., and . ED&TC, page 84-89. IEEE Computer Society, (1997)Intelligent Methods for Test and Reliability., , , , , , , , , and 25 other author(s). DATE, page 969-974. IEEE, (2022)Robust Reconfigurable Scan Networks., , and . DATE, page 1149-1152. IEEE, (2022)Reliability Considerations forMechatronic Systems on the Basis of a State Model., , , and . ARCS Workshops, volume P-41 of LNI, page 106-112. GI, (2004)