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Foreword., , и . J. Circuits Syst. Comput., 26 (8): 1702001:1-1702001:1 (2017)ASIC Architecture and Implementation of RED Scheduler for Mixed-Criticality Real-Time Systems., и . MIXDES, стр. 83-88. IEEE, (2020)CCII+ current conveyor based BIC monitor for IDDQ testing of complex CMOS circuits., и . ED&TC, стр. 266-270. IEEE Computer Society, (1997)Novel architecture of a digital neuron for FFNN employing special multiplication., , , , и . ECAI, том 263 из Frontiers in Artificial Intelligence and Applications, стр. 933-938. IOS Press, (2014)A new efficient sorting architecture for real-time systems., и . MECO, стр. 1-4. IEEE, (2017)Low-Leakage ESD Structures in 130nm CMOS Technology., , и . RADIOELEKTRONIKA, стр. 1-4. IEEE, (2020)International Symposium on Design and Diagnostics of Electronic Circuits and Systems., , , , , , , , и . ITC, стр. 1-4. IEEE, (2019)Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology., , , , и . DDECS, стр. 40-45. IEEE, (2016)A novel impedance calculation method and its time efficiency evaluation., , , , и . DDECS, стр. 99-103. IEEE Computer Society, (2014)Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies., , , и . DDECS, стр. 395-396. IEEE Computer Society, (2011)