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Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning.

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Industrial clock design.. ISPD, page 139-140. ACM, (2009)HYTECH: A Model Checker for Hybrid Systems., , and . CAV, volume 1254 of Lecture Notes in Computer Science, page 460-463. Springer, (1997)Supporting sequential assumptions in hybrid verification., , , , and . ASP-DAC, page 1035-1038. ACM Press, (2005)Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems., , , and . Hybrid Systems, volume 736 of Lecture Notes in Computer Science, page 209-229. Springer, (1992)Coverage Estimation for Symbolic Model Checking., , , and . DAC, page 300-305. ACM Press, (1999)Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System., , , , , and . ICCAD, page 1-9. IEEE, (2023)Abstraction Refinement.. ATVA, volume 3299 of Lecture Notes in Computer Science, page 7. Springer, (2004)Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure., , , , and . ISQED, page 344-349. IEEE Computer Society, (2007)Automatic Symbolic Verification of Embedded Systems., , and . IEEE Trans. Software Eng., 22 (3): 181-201 (1996)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning., , , and . ISPD, page 15-21. ACM, (2017)