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Disambiguation of "Béchennec, Jean-Luc"

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PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation.

, , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 262-265. Springer, (1999)

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Jean-Luc Rebière

Jean-Luc Wolfender

Jean-Luc Boevé

Jean-Luc Wagner

Jean-Luc Régnier

 

Other publications of authors with the same name

A Parallel Algorithm for 3D Geometry Transformations in OpenGL., , , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 659-662. Springer, (1999)Formal Model-Based Synthesis of Application-Specific Static RTOS., , , and . ACM Trans. Embed. Comput. Syst., 16 (4): 97:1-97:25 (2017)Testing Real-Time Systems With Runtime Enforcement., , , , and . IEEE Des. Test, 35 (4): 31-37 (2018)Hardware runtime verification of embedded software in SoPC., , , , and . SIES, page 171-176. IEEE, (2016)HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems., , and . AHS, page 249-256. IEEE, (2018)Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces., , and . EUROMICRO, page 409-. IEEE Computer Society, (1997)Improving processor hardware compiled cycle accurate simulation using program abstraction., , , and . SimuTools, page 186-194. ICST/ACM, (2014)Evaluation of High Performance Multicache Parallel Texture Mapping., , and . International Conference on Supercomputing, page 289-296. ACM, (1998)STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems., , , , and . ACM Trans. Embed. Comput. Syst., 14 (4): 66:1-66:25 (2015)Increasing hardware data prefetching performance using the second-level cache., , and . J. Syst. Archit., 48 (4-5): 137-149 (2002)