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Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis., , and . ASPLOS (4), page 87-107. ACM, (2023)Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights, , , , , and . (2020)cite arxiv:2007.00864.RAMP: resource-aware mapping for CGRAs., , and . DAC, page 127:1-127:6. ACM, (2018)Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level., , , , , , , , , and 5 other author(s). DATE, page 1-10. IEEE, (2023)URECA: Unified register file for CGRAs., , and . DATE, page 1081-1086. IEEE, (2018)SPX64: A Scratchpad Memory for General-purpose Microprocessors., , , , , , , , and . ACM Trans. Archit. Code Optim., 18 (1): 14:1-14:26 (2021)Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems., , , , , , and . VTS, page 1-14. IEEE, (2022)LASER: A hardware/software approach to accelerate complicated loops on CGRAs., , , and . DATE, page 1069-1074. IEEE, (2018)dMazeRunner: Optimizing Convolutions on Dataflow Accelerators., , , , and . ICASSP, page 1544-1548. IEEE, (2020)