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A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.

J. Lin, and J. Yuan. Neurocomputing, (2020)

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Jiann-Sheng Wu

Jiann-Trzuo Lin

Jiann-Chyuan Lin

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge.W. Yang, J. Yuan, B. Krishnan, A. Tzou, and W. Yeh. IRPS, page 1-5. IEEE, (2020)Optimization of NULL convention self-timed circuits.S. Smith, R. DeMara, J. Yuan, D. Ferguson, and D. Lamb. Integr., 37 (3): 135-165 (2004)Emerging Technology-Based Design of Primitives for Hardware Security.Y. Bi, K. Shamsi, J. Yuan, P. Gaillardon, G. Micheli, X. Yin, X. Hu, M. Niemier, and Y. Jin. ACM J. Emerg. Technol. Comput. Syst., 13 (1): 3:1-3:19 (2016)Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs.Q. Alasad, and J. Yuan. ICCD, page 341-344. IEEE Computer Society, (2017)Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.Y. Bi, P. Gaillardon, X. Hu, M. Niemier, J. Yuan, and Y. Jin. ATS, page 342-347. IEEE Computer Society, (2014)Security analysis of computing systems from circuit-architectural perspective.S. Taheri, and J. Yuan. DSC, page 166-173. IEEE, (2017)Thermal reliability of VCO using InGaP/GaAs HBTs.X. Liu, J. Yuan, and J. Liou. Microelectron. Reliab., 51 (12): 2147-2152 (2011)ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests.W. Yang, N. Stoll, and J. Yuan. IRPS, page 1-5. IEEE, (2020)Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.J. Di, J. Yuan, and R. DeMara. Integr., 39 (2): 90-112 (2006)NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.S. Smith, R. DeMara, J. Yuan, M. Hagedorn, and D. Ferguson. J. Syst. Archit., 47 (12): 977-998 (2002)

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Disambiguation of "Yuan, Jiann-Shiun"

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A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.

Please choose a person to relate this publication to

Jiann-Sheng Wu

Jiann-Trzuo Lin

Jiann-Chyuan Lin

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yuan, Jiann-Shiun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.

Please choose a person to relate this publication to

Jiann-Sheng Wu

Jiann-Trzuo Lin

Jiann-Chyuan Lin

Fang Yuan

Jing Yuan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.