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Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters., , , , , and . CCGRID, page 131-141. IEEE, (2020)Network footprint reduction through data access and computation placement in NoC-based manycores., , , and . DAC, page 181:1-181:6. ACM, (2015)Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors., , , and . SoCC, page 77-78. IEEE, (2006)Using Task Recomputation During Application Mapping in Parallel Embedded Architectures., , and . CDES, page 29-35. CSREA Press, (2006)The design and use of simplepower: a cycle-accurate energy estimation tool., , , and . DAC, page 340-345. ACM, (2000)Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression., , and . CODES+ISSS, page 87-92. ACM, (2005)Hybrid-comp: A criticality-aware compressed last-level cache., , , and . ISQED, page 25-30. IEEE, (2018)Application mapping for chip multiprocessors., , , and . DAC, page 620-625. ACM, (2008)