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Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors., , , and . ISQED, page 71-76. IEEE, (2022)FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning., , , , , , , , , and . ASP-DAC, page 19-25. IEEE, (2020)Clock network minimization methodology based on incremental placement., , , , , and . ASP-DAC, page 99-102. ACM Press, (2005)Physical design techniques for optimizing RTA-induced variations., , , and . ASP-DAC, page 745-750. IEEE, (2010)Lightning Talk: Power and Performance Reconciliation - from Tradeoff to Win-Win.. DAC, page 1-2. IEEE, (2023)A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing., and . ICCD, page 282-. IEEE Computer Society, (2003)Dynamic voltage and frequency scaling for shared resources in multicore processor designs., , , , , , , and . DAC, page 114:1-114:7. ACM, (2013)Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding., , , , and . ISQED, page 627-632. IEEE Computer Society, (2008)Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders., , and . ISQED, page 749-754. IEEE Computer Society, (2007)Efficient Model Update for General Link-Insertion Networks., , and . ISQED, page 43-50. IEEE Computer Society, (2006)