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A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.

C. Huang, K. Ma, S. Chen, J. Fan, N. Sun, H. Yang, and X. Li. CICC, page 1-2. IEEE, (2024)

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Yang Yang

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A "Near-the-Best" System-Level Design Methodology of Multi-Core H.264 Video Decoder Based on the Parallelized Multi-Core Simulator.B. Xia, F. Qiao, Z. Du, D. Zhu, and H. Yang. Journal of Circuits, Systems, and Computers, (2012)Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET.H. Luo, H. Yang, and L. Rong. APCCAS, page 956-959. IEEE, (2006)Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules.Y. He, J. Yue, Y. Liu, and H. Yang. ASP-DAC, page 813-818. ACM, (2021)A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC.Y. Huang, Y. He, J. Yue, H. Yang, and Y. Liu. ASP-DAC, page 126-131. ACM, (2021)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.Y. Chen, M. Lee, G. Dai, M. Zhou, N. Challapalle, T. Wang, Y. Yu, Y. Liu, Y. Wang, H. Yang and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.Q. Zhao, W. Sun, J. Zhao, J. Zhao, H. Yao, T. Ho, X. Guo, H. Yang, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (11): 2043-2057 (2019)Explore-Bench: Data Sets, Metrics and Evaluations for Frontier-based and Deep-reinforcement-learning-based Autonomous Exploration.Y. Xu, J. Yu, J. Tang, J. Qiu, J. Wang, Y. Shen, Y. Wang, and H. Yang. ICRA, page 6225-6231. IEEE, (2022)An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.S. Zeng, K. Guo, S. Fang, J. Kang, D. Xie, Y. Shan, Y. Wang, and H. Yang. DSP, page 1-5. IEEE, (2018)A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.B. Xia, F. Qiao, H. Yang, and H. Wang. ISQED, page 191-197. IEEE, (2010)TSV-aware topology generation for 3D Clock Tree Synthesis.W. Liu, H. Du, Y. Wang, Y. Ma, Y. Xie, J. Quan, and H. Yang. ISQED, page 300-307. IEEE, (2013)

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Disambiguation of "Yang, Huazhong"

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A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Huazhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS.