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Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).

K. Hosokawa, P. Narayanan, S. Ambrogio, H. Tsai, C. Mackin, A. Fasoli, A. Friz, A. Chen, J. Luquin, K. Spoon, G. Burr, and S. Lewis. ISCAS, page 1-5. IEEE, (2021)

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Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.S. Jain, H. Tsai, C. Chen, R. Muralidhar, I. Boybat, M. Frank, S. Wozniak, M. Stanisavljevic, P. Adusumilli, P. Narayanan and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 114-127 (2023)Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory.P. Narayanan, A. Fumarola, L. Sanches, K. Hosokawa, S. Lewis, R. Shelby, and G. Burr. IBM J. Res. Dev., 61 (4-5): 11:1-11:11 (2017)Towards a framework for designing applications onto hybrid nano/CMOS fabrics.C. Dezan, C. Teodorov, L. Lagadec, M. Leuchtenburg, T. Wang, P. Narayanan, and C. Moritz. Microelectron. J., 40 (4-5): 656-664 (2009)Overview of the IBM Neural Computer Architecture.P. Narayanan, C. Cox, A. Asseman, N. Antoine, H. Huels, W. Wilcke, and A. Ozcan. CoRR, (2020)Equivalent-accuracy accelerated neural-network training using analogue memory.S. Ambrogio, P. Narayanan, H. Tsai, R. Shelby, I. Boybat, C. di Nolfo, S. Sidler, M. Giordano, M. Bodini, N. Farinha and 4 other author(s). Nat., 558 (7708): 60-67 (2018)Parameter variation sensing and estimation in nanoscale fabrics.J. Zhang, M. Rahman, P. Narayanan, S. Khasanvis, and C. Moritz. J. Parallel Distributed Comput., 74 (6): 2504-2511 (2014)CMOS Control Enabled Single-Type FET NASIC.P. Narayanan, M. Leuchtenburg, T. Wang, and C. Moritz. ISVLSI, page 191-196. IEEE Computer Society, (2008)Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.P. Vijayakumar, P. Narayanan, I. Koren, C. Krishna, and C. Moritz. NANOARCH, page 181-188. IEEE Computer Society, (2011)Validating cascading of crossbar circuits with an integrated device-circuit exploration.P. Narayanan, C. Moritz, K. won Park, and C. Chui. NANOARCH, page 37-42. IEEE Computer Society, (2009)Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.C. Mackin, P. Narayanan, S. Ambrogio, H. Tsai, K. Spoon, A. Fasoli, A. Chen, A. Friz, R. Shelby, and G. Burr. IRPS, page 1-10. IEEE, (2020)

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Disambiguation of "Narayanan, Pritish"

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Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).

Please choose a person to relate this publication to

Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Pritish"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).

Please choose a person to relate this publication to

Pritish Sinha

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).