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A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware., , и . ISCAS, стр. 161-164. IEEE, (2007)Improved multicast switch architecture for optical cable television and video surveillance networks., и . ISCAS (4), стр. 221-224. IEEE, (2004)Buffer implementation for Proteo network-on-chip., , и . ISCAS (2), стр. 113-116. IEEE, (2003)A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck., , , и . FPL, стр. 487-490. IEEE, (2008)MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver., , и . J. Syst. Archit., 60 (1): 140-149 (2014)Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking., , и . DATE, стр. 264-267. ACM, (2008)Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices., , и . DATE, стр. 147-152. EDA Consortium, San Jose, CA, USA, (2007)Design of a matched filter for timing synchronization., и . DASIP, стр. 247-251. IEEE, (2013)Efficient FFT pruning algorithm for non-contiguous OFDM systems., , и . DASIP, стр. 144-149. IEEE, (2011)Training communication skills in project-oriented microelectronics courses., , , и . EWME, стр. 16-20. IEEE, (2014)